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Wafer Backside Spin-Process Contamination Elimination for Advanced Copper Device Applications
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Semiconductor Fabtech, January 2000
Authors: Ernst Gaulhofer, Heinz Oyrer, SEZ AG
Bing-Yue Tsui, National Chiao Tung University, Hsinchu, Taiwan
Abstract:
Wafer cleaning is the most frequently repeated process in semiconductor manufacturing and with an industry- wide move to copper interconnects, contamination control requirements are extremely critical. Interconnect delay begins to dominate overall device delay at 0.18µm, making low-resistance copper attractive and high reliable cleaning essential, especially considering the expense of frequent contamination monitoring. Successful integration requires stringent control of cross contamination from deposition equipment (PVD, CVD, and electroplating tools), CMP equipment, and all metrology tools shared by copper processed wafers. Additionally, the exclusion zone on the front-side of the wafer is another source of cross contamination. Semiconductor wafer fabrication companies insist in a method that utilizes existing equipment for development of copper applications.Therefore, a highly effective method of eliminating copper from the wafer backside, bevel and edge must be implemented. The combination of edge cleaning and the edge evaluation is available for introducing not only Cu but new exotic materials such as Ta2O5, BST and Ru, too.
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