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A Novel Wafer Backside Spin-Process Contamination Elimination Technique for Copper Production Applications (October 1999)
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Published at the 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference
and Workshop (ASMC)
Patrick S. Lysaght, Israel Ybarra, Ted Doros, James V. Beach, SEMATECH
Harry Sax, James L. Mello, Michael G. West, Gaurav Gupta, SEZ America Inc.
Abstract - Interconnect delay begins to dominate overall device delay at 180 nm, making low resistivity copper highly desirable. Copper migrates very quickly in silicon; therefore, successful integration requires stringent control of copper cross-contamination from deposition equipment, electroplating tools, chemical-mechanical polishing (CMP) equipment, and all metrology tools shared by copper processed wafers. In this paper, data illustrating a highly effective means of eliminating copper from the wafer backside, bevel/edge, and frontside edge exclusion zone (0.5 mm – 3 mm), is presented. The data, obtained within the framework of standard and experimental copper/low-k device production at SEMATECH, quantifies the benefits of implementing the SEZ Spin-Process contamination elimination (SpCE) clean operation. Furthermore, this data confirms the feasibility of utilizing existing (non-copper) process equipment in conjunction with the development of copper applications by verifying the reliability and cost effectiveness of SpCE functionality ....
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