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Spin-Etch Planarization Process for Copper Damascene Interconnects
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Published at the Semicon Japan - 1999
J. Levert, Allied Signal Electronic Materials, 1349 Moffett Park Dr. 94089, USA
S.Mukherjee, Allied Signal Electronic Materials, 1349 Moffett Park Dr. 94089, USA
D. DeBear, SEZ America, Inc., 4824 South 40th St., Phoenix, AZ 85040, USA
Abstract - A copper damascene architecture will likely be common in future integrated circuit metallization schemes. In the dual-damascene process, the electro-deposition of copper is made simultaneously into inlaid vias holes and line trenches. An excess of copper is deposited in the field areas to achieve a complete filling of the vias and trenches of different sizes. The excess copper is typically removed by a chemical mechanical planarization (CMP) process designed to leave metal lines in place in trenches etched into the dielectric. The CMP process has some inherent disadvantages such as particle contamination, scratching of dielectric and metal surfaces, and pressure induced mechanical damage.
Spin Etch Planarization (SEP) presented in this work is based on the principles of controlled chemical etching of metals. Spin-Etch Planarization can eliminate some of the disadvantages associated with CMP processing.
During SEP, the wafer is suspended horizontally on a nitrogen cushion above a rotating chuck. The substrate is held in place laterally with locking pins on the wafer edge. As the chuck and wafer are spun, wet etch chemistries are dispensed onto the wafer. A planar final surface is achieved by using an appropriate etching solution and the spinning of the wafer while removing the excess copper ....
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