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Wafer Thinning: Techniques for Ultra-thin Wafers
Advanced Packaging, March 2003
Authors: Manfred Reiche and Gerald Wagner
Abstract:
As electronics applications shrink in size, integrated circuit (IC) packaged devices must be reduced both in footprint and thickness. The main motivation for the development of smaller packages is the demand for portable communications devices, such as memory cards, smart cards, cellular telephones and portable computing.1
One of many crucial aspects in developing ultra-thin packages is die thickness. The reduction of the chip thickness, however, is combined with an increasing wafer diameter, but larger wafer diameters require thicker silicon to withstand wafer manufacturing. The requirement of an increasing thickness of the wafers during processing and the contrasting interest of thinner die makes thinning techniques more and more important.
Because the thinning of the whole wafer at the back end, i.e., after the complete device processing on the front side, is the most effective way for preparing ultra-thin chips, new or improved thinning techniques are necessary. Time- and cost-efficient processes are required, and the thickness tolerance should be ≤1µm even at final wafer thickness of 20 µm.
About Authors:
Manfred Reiche, Ph.D., scientific staff member, may be contacted at Max-Planck Institut für Mikrostrukturphysik, Weinberg 2, D-06120 Halle, Germany, 49 345 558250.
Gerald Wagner, Ph.D., process application manager, may be contacted at SEZ AG, Draubodenweg 29, A-9500 Villach, Austria, 43 4242 204; E-mail: g.wagner@at.sez.com.
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