Dr. Mukesh V. Khare

received the M.S., M. Phil. and Ph.D. degrees from Yale University in 1995, 1997 and 1999 respectively. He joined the IBM Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY, in 1998 and has been actively perusing research and development in CMOS technology at various positions. He led the engineering team towards development and qualification of the 90nm SOI technology all the way from the basic definition to the transfer in 300mm manufacturing Fab and volume production. Dr. Khare managed the second generation 65nm and the 45nm SOI device design department at IBM. He was the senior manager leading 32nm Silicon Technology Research at IBM's Watson Research Center. Dr. Khare is now the project manager leading introduction and volume production of High-K/Metal Gate technology in 300mm Fab at IBM. He has authored and co-authored more than 35 research papers of which 15 papers were presented at the IEDM and VLSI technology conferences.

Dr. Khare’s research interest include development of advanced devices and structures for CMOS technology, process integration for integrated circuits, SRAM and device reliability for acceptable minimum and maximum operating voltage, gate dielectric development and technology/design interaction.