|
SEZ America Launches US 300 mm Lab
State-of-the-art Facility Gives Worldwide IC Manufacturers An Edge in 300 mm Wafer Processing
PHOENIX, April 30, 2002 -- The SEZ Group continues to show leadership and support for the future of integrated circuit (IC) manufacturing with its groundbreaking achievements in wafer surface preparation, and now with the opening of its first 300 mm applications lab in the US. Located in Phoenix, Ariz., the 3000 square foot lab will be a resource for SEZ and its customers and partners worldwide to test 300 mm wafer cleaning processes.
"300 mm is here, and the ability to provide complete 300 mm testing capability is still a rarity," stated Jim Mello, vice president of operations at SEZ America. "This lab will give our customers and technology partners an edge in turn around time, with more valuable and timely data, and will greatly speed customers' development and introduction of faster, more powerful chips."
"In this extremely fierce and competitive market, it is critical for our customers to reach high yield and volume manufacturing to meet market windows for the next-generation of chips," commented Kurt Lackenbucker, chief marketing officer of the SEZ Group. "This facility will enable SEZ to be a value-add partner, working closely together with customers to combat cleaning challenges and find the most effective solutions for their processes."
300 mm Cleaning Challenges
Wafer cleaning and surface preparation technology has evolved with the implementation of new materials and processes. The focus continues on maximizing the quality of the gate dielectric, especially as the industry moves towards high-k logic gates, which present new challenges for decontamination of wafer backsides and edge bevels. Smaller chip outlines and higher speeds required from the chip have also led to the introduction of low-k dielectrics and copper (Cu) conductor schemes, which create additional challenges. They too must also be cleaned, rinsed of the cleaning solution and dried, all without affecting the k value inherent to the material.
New MPU and DRAM materials have increased the need for highly selective etching chemistries and processes, and increased attention is being given to backside particles due to their effect on lithography alignment and cross-contamination to adjacent wafer front sides in cleaning tools.
Lab Capabilities Combat Challenges
Currently running three-four demos per week, SEZ is primarily testing customer wafers for stress relief, polymer removal and wafer thinning. Additional capabilities include backside film removal for pre-litho yield enhancement, backside and bevel clean for Cu decontamination and frontside polymer clean for metal line, via holes and Cu dual damascene technologies.
The lab has complete 300 mm capability, featuring 1253 square feet of class 10 cleanroom space and currently houses 20 pieces of process equipment. The facility incorporates SEZ's Spin-Processors 101, 203, 303 and the 1300 will be installed in May. SEZ's investment in the new facility also includes the Axcelis 200ES Asher tool and metrology equipment from Tencor, FEI, Philips, ADE, Nikon, Luxtron, Rigaku, Veeco and CDE RESMAP.
The Tencor SP1 metrology tool is capable of detecting less than 60 nm light point defects on non-patterned 200 mm and 300 mm wafers. 300 mm tools include FEI's Expedia dual beam single-wafer SEM/FIB with FOUP and Philips' PZ2000-300 dual wavelength ellipsometer.
Single-Wafer Portfolio
SEZ's single-wafer spin-processing cleaning technology capabilities include polymer clean BEOL and pre and post clean FEOL, as well as post CMP clean. SEZ's etching and stripping technology includes capabilities for advanced frontside and backside etching, thinning, stripping, cleaning and wafer reclaim. Backside/bevel etch technology includes backside film removal and backside and bevel clean. Substrate etch tools cover wafer thinning, stress relief and surface conditioning capabilities.
300 mm Batch Technology
With conventional batch processing expected to remain effective for high-volume products, especially memory markets, SEZ will add 300 mm wet bench capability to its product portfolio in the coming months. This is in line with the company's overall 300 mm strategy as well as its recently announced specialization in the entire wet surface preparation market, providing a complete 300 mm solutions portfolio for customers' single wafer and batch processing needs. The company's first generation of 300 mm equipment will focus on pre-clean FEOL (pre-diffusion clean, RCA clean, pre-gate clean) and etching (nitride etch) with the capability of spiking and diluted chemistries
About SEZ
The SEZ Group is a leading supplier of wet wafer surface preparation equipment to the global semiconductor manufacturing industry. The company's breakthrough proprietary Spin-Processor technology forms the basis of a broad portfolio of single wafer backside and frontside wafer surface conditioning products for semiconductor chipmakers worldwide. Additionally, the company offers a complete range of wet bench equipment for batch processing. SEZ maintains development, manufacturing, sales, marketing and service operations in Europe, Asia and North America. Registered in Zurich, Switzerland, SEZ Holding AG is listed on the Swiss Exchange under the symbol (SWX: SEZN).
.
|