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Released by Sematech
International SEMATECH Qualifies Porous Low-K Dual Damascene Process on 300 mm
Consortium Becomes First Site for 300 mm Ultra Low-K Process Flow Capability
International SEMATECH’s (ISMT) Interconnect Division announced this week that it has qualified its low-k baseline process on 300 mm tools. This achievement means that for the first time at ISMT dual damascene copper/low-k processing can take place using 300 mm equipment.
“With this baseline in place, we can continue to evaluate all of the many different kinds of low-k materials on a 300 mm platform to generate the data that helps our member companies and the industry make informed decisions about their next low-k material,” said Navjot Chhabra, Director of Interconnect at ISMT.
“This success in integrating low-k materials on 300 mm represents a major step in our ability to continue to provide our member companies and partners with advanced materials screening and development,” said Chhabra. “It also gives ISMT full 300 mm processing capability using various low-k materials.”
Located in ISMT’s cleanroom (Advanced Technology Development Facility or ATDF), the processing capability on 300 mm wafers comes just six months after qualification of the flow on 200 mm, and comes two months after qualifying a 300 mm SIO2 flow. The material used in the 300 mm flow was a methyl silicate-based dielectric with a K value of ~2.2. ISMT’s baseline is a true dual damascene process using standard copper electroplating and conventional CMP (chemical mechanical planarization). The process used technologies supplied by Applied Material, JSR, Novellus, SEZ and Tokyo Electron.
ISMT is now positioned to provide the infrastructure and the capability to develop processes and support materials for advanced low-k materials at 300 mm using the most advanced tools and processes for the 65 nm node and beyond. International SEMATECH will run this process flow routinely to continually monitor unit processes. Much of the development to date for the 65 nm node has taken place on 200 mm wafers. As a result of this advance, however, dual damascene low-k copper can now be tested on 300 mm equipment
“This milestone will help ease the transition into manufacturing,” says Ken Monnig, associate director of Interconnect. “The development conducted from now on will be done on the same tools and wafer size that the end user will have in his fab at the 65 nm node.”
International SEMATECH (ISMT) is a global semiconductor technology development consortium that has effectively represented the semiconductor manufacturing industry on innovation issues since 1988; its members are Agere Systems, AMD, Hewlett- Packard, Hynix, IBM, Infineon, Intel, Motorola, Philips, STMicroelectronics, Texas Instruments and TSMC. ISMT conducts state-of-the-art research, and is a highly regarded technology partner whose mission is to promote the interests common to all chipmakers. It has extensive experience collaborating with equipment and materials suppliers, as well as government and academic research centers to refine the tools and technology necessary to produce future generations of chips. Additional information may be found at www.sematech.org.
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